A typical memory system includes a memory storage device and a memory controller. Memory storage devices can include, without limitation, randomly accessible memory (RAM) devices and memory storage devices which include storage media such as magnetic and/or optical disks. Dynamic RAM (DRAM), is an example of a memory storage device which is commonly used in computer systems.
Memory controller devices typically receive memory access instructions from a processor unit such as, for example, a central processing unit (CPU). Program instructions executed by a processor typically require that memory access instructions issued to a memory controller be executed by the memory controller in the particular sequence in which the memory access instructions are received by the memory controller. For example, a read instruction which retrieves data stored in a memory location written to by a previously issued write instruction is expected to retrieve the data stored in execution of the write instruction. In other words, the previously write instruction is expected to execute before the subsequently issued read instruction. If the relative order of execution of the write and read instructions is not preserved, the data retrieved by execution of the read instruction varies depending on the relative order of execution of the write and read instructions. Such leads to unpredictable behavior of computer processes. Therefore, memory access operations are typically performed in sequence to maintain data integrity and computer process predictability.
In a split memory access transaction, a single memory access instruction can be issued in multiple parts. For example, a request for memory access and corresponding memory address can both be issued from a processor to a memory controller in a first transaction and data corresponding to the request and memory address can be issued from the processor to the memory controller in a second, subsequent transaction. Such split memory access transactions are typically split write instructions since a write instruction typically requires both a destination memory address and write data to be written to the destination address. Accordingly, the destination address can be transmitted to a memory controller along with an instruction specifying a write operation in a first transaction while the write data can be transmitted to the memory controller in a subsequent transaction. Read instructions typically specify a source address and an instruction specifying a read operation. Transmission of read data to the memory controller is generally unnecessary since the data transfer of the read operation is from the memory to the processor. Accordingly, read instructions are typically considered complete by the memory controller since all information required to execute a read instruction is received when the read request and source address are received.
A split write instruction typically requires that the write instruction is complete prior to execution of the write instruction by the memory controller. Specifically, the memory controller generally cannot execute a split write instruction until the requisite write data is received in a subsequent transaction. Because the write data in a split write instruction is often provided in a subsequent transaction than the write instruction and destination address, processing of a split write instruction can require a write data stall period. As used herein, a write data stall period refers to a period of inactivity of a memory controller while the memory controller waits for receipt of the write data of a split write instruction. Conversely, read instructions in split transaction systems, which include a read request and a read address, can be processed by the memory controller immediately without any stall period.
Split transactions enhance memory access efficiency by allowing a memory system to initiate a memory write instruction, gather the necessary corresponding write data from any of a number of sources, and complete processing of the memory write instruction when the requisite write data is subsequently received. However, because memory access operations are typically executed in sequence to preserve data integrity, subsequent memory access instructions which are complete and ready for execution, including read instructions, must generally wait for execution of preceding split write instructions which cannot be executed until the requisite write data is received by the memory controller. This blocking of subsequent memory access instructions pending receipt of write data corresponding to a previously received split write instruction represents a significant inefficiency in conventional split transaction memory control systems.
What is needed is a mechanism for further improving the efficiency and throughput of memory controllers which process a sequence of split memory access instructions wherein data integrity is preserved.